FLASHREF v1.2  2021-08-19 polprog
v1.0: Initial version 2021-08-19
v1.1: Added NOR FLASH series info 2021-08-19
v1.2: Added voltages, more types, serial pinouts, more notes 2021-08-19
v1.2.1: Added notes about "Boot block flash" memories 2021-08-19
v1.3: Added FWH/LPC flash information 2022-01-05

Guide to memory chip replacements and pinouts. See also ROMref.txt for older
chips.
The latest version of this file can be found
at https://polprog.net/papiery/flashref.txt

General notes:
- It's possible to replace a smaller flash with larger flash. Repeat data in
  this case. This way the data will be the same no matter what state the higher
  address pins are in.
- You can replace a 16 bit memory with two 8 bit memories in parallel, one chip
  then handles DQ0-DQ7 and the other DQ8-DQ15. They should be the same type and
  access time.
- PLCC pinouts follow the same pattern (for ex. WE# on 27C010 becomes A18 on
  27C040)
- Always confirm pinout with datasheet
- For 24 pin chip compatiability see ROMref.txt

Part no syntax: [manuf. prefix]<series><size>-<access time>

Series:
 27, 27C  = EPROM (UV eraseable/OTP) 5V
 27W, 27V = EPROM (UV eraseable/OTP) 3.3V
 28C      = EEPROM 5V
 28F, 29C, 29F = FLASH EEPROM 3.3V (and lower)
 39F, 39SF     = FLASH 5V
 39LF, 39VF    = FLASH 3.3V
 49F, 49HF     = FLASH 5V
 49LF     = LPC or FWH FLASH 3.3V
 52, 62   = SRAM 5V
 48Z, DS12, XS22 = NVRAM
 24C, 25C, 93C   = Serial EERPOM (SPI/I2C/Microwire) 5V
 24L, 25L, 93LC  = Serial EEPROM (SPI/I2C/Microwire) <5V
 47L, 47C, 48L   = Serial EERAM (I2C 3.3V/I2C 5V/SPI 3.3V)
 FM25V, 85RC     = Serial F-RAM (ferroelectric RAM)
 85R      = Paralell FRAM

Size code:
 01 = 1 KBit (128 x 8)
 02 = 2 KBit (256 x 8)
 04 = 4 KBit (512 x 8)
 08 = 8 KBit (1k x 8)
 16 = 16 KBit (2k x 8)
 32 = 32 KBit (4k x 8)
 64 = 64 KBit (8k x 8)
 128 = 128 KBit (16k x 8)
 256 = 256 KBit (32k x 8)
 512 = 512 KBit (64k x 8)
 1001 or 010 = 1 MBit (128k x 8)
 1024 or 102 = 1 MBit (64k x 16)
 2001 or 020 = 2 MBit (256k x 8)
 2048 or 202 = 2 MBit (128k x 16)
 4001 or 040 = 4 MBit (512k x 8)
 4096 or 402 = 4 MBit (256k x 16)
 8001, 080 or 801 = 8 MBit (1M x 8)
 8192 = 8 MBit (1M x 8 or 512k x 16)
 016 or 160 = 16 MBit (2M x 8 or 1M x 16) see note below
 322 or 320 = 32 MBit (2M x 16)


 Note: Different 016 and 160 chips have different organization (8bit or 16 bit)
 or support reconfigurable organization (BYTE# pin switches addressing. Q15A-1
 pin behaves as address LSB when in BYTE mode. )

(not an exhaustive list. Manufacturers sometimes make direct replacements with
retronamed parts)

Access time:
 45 = 45 ns
 60 = 60 ns
 70 = 70 ns
 90 = 90 ns
 10 = 100 ns
 12 = 120 ns
 15 = 150 ns
 20 = 200 ns
 25 = 250 ns


DIP pinouts
------------

32 pin chips:
 size = 010, 020, 040, 080
 1. WE# = WE# for EEPROM and RAM, PGM# for EPROM
 2. 29F010: pin 1 = NC;
    29F020: Sold as 29F002, pin 1 = RESET#
    29F040: pin 1 = A18, pin 31 = WE#
    29F080: 44 pin chip
 3. OE# doubles as Vpp for x=8
 4. Flash memories sold as "Boot block flash" have an extra control pin labeled
    RP# (Powerdown, pin 30) which needs to be pulled to Vcc in order to make the
    flash work. Usually marked as "B" appended after size.
 Common FLASH replacements: AM29F0x0 (AMD) up to 040, see note 2
                            W27C0x0 (Winbond) up to 040
                            SST39SF0x0 (SST) up to 040
x=1  x=2  x=4  x=8         x=1  x=2  x=4  x=8
                   .--_--.
Vpp  Vpp  Vpp  A19 |1  32| Vcc  Vcc  Vcc  Vcc
A16  A16  A16  A16 |     | WE#  WE#  A18  A18
A15  A15  A15  A15 |     | NC   A17  A17  A17
A12  A12  A12  A12 |     | A14  A14  A14  A14
A7   A7   A7   A7  |     | A13  A13  A13  A13
A6   A6   A6   A6  |     | A8   A8   A8   A8
A5   A5   A5   A5  |     | A9   A9   A9   A9
A4   A4   A4   A4  |     | A11  A11  A11  A11
A3   A3   A3   A3  |     | OE#  OE#  OE#  OE#
A2   A2   A2   A2  |     | A10  A10  A10  A10
A1   A1   A1   A1  |     | CE#  CE#  CE#  CE#
A0   A0   A0   A0  |     | DQ7  DQ7  DQ7  DQ7
DQ0  DQ0  DQ0  DQ0 |     | DQ6  DQ6  DQ6  DQ6
DQ1  DQ1  DQ1  DQ1 |     | DQ5  DQ5  DQ5  DQ5
DQ2  DQ2  DQ2  DQ2 |     | DQ4  DQ4  DQ4  DQ4
Vss  Vss  Vss  Vss |16 17| DQ3  DQ3  DQ3  DQ3
                   '-----'


28 pin chips:
 size = 64,128,256,512
 1. PGM# = WE# for RAM
 2. OE# doubles as Vpp for 512
 Common FLASH Replacements: W27C512 (Winbond), SST27SF256 (SST),
                            SST27SF512 (SST)

 64  128  256  512          64  128  256  512
                   .--_--.
Vpp  Vpp  Vpp  A15 |1  28| Vcc  Vcc  Vcc  Vcc
A12  A12  A12  A12 |     | PGM# PGM# A14  A14
A7   A7   A7   A7  |     | NC   A13  A13  A13
A6   A6   A6   A6  |     | A8   A8   A8   A8
A5   A5   A5   A5  |     | A9   A9   A9   A9
A4   A4   A4   A4  |     | A11  A11  A11  A11
A3   A3   A3   A3  |     | OE#  OE#  OE#  OE#
A2   A2   A2   A2  |     | A10  A10  A10  A10
A1   A1   A1   A1  |     | CE#  CE#  CE#  CE#
A0   A0   A0   A0  |     | Q7   Q7   Q7   Q7
Q0   Q0   Q0   Q0  |     | Q6   Q6   Q6   Q6
Q1   Q1   Q1   Q1  |     | Q5   Q5   Q5   Q5
Q2   Q2   Q2   Q2  |     | Q4   Q4   Q4   Q4
Vss  Vss  Vss  Vss |14 15| Q3   Q3   Q3   Q3
                   '-----'

24 pin chips:
size = 16, 32
There are various incompatible parts. See ROMref.txt for more info.
Common replacements: 27Cxx can be replaced by EEPROM AT28Cxx (Atmel/Microchip)

I2C and SPI memories
---------------------

1. Reading in-circuit not always possible (other chips may be driving the bus)
   In this case, force reset of other chips or remove from circuit
2. Vcap for I2C EERAM (backup capacitor): A0 for I2C, WP# for SPI
3. Pinouts identical to SOIC packages

Replacement: Replace with same or larger chip of the same family.

SPI                    I2C
    .--_--.               .--_--.
CS# |1   8| Vcc        A0 |1   8| Vcc
SO  |     | HOLD#      A1 |     | WP
WP# |     | SCK        A2 |     | SCL
Vss |4   5| SI        Vss |4   5| SDA
    '-----'               '-----'

    .--_--.
CS# |1  14| Vcc
SO  |     | HOLD#
NC  |     | NC
NC  |     | NC
NC  |     | NC
WP# |     | SCK
Vss |7   8| SI
    '-----'


PLCC Pinouts
-------------

PLCC32 THT socket pinout:

Top view:               Bottom view:

    .--------------.    .---------------.
  .'  4  2 32 30    |  |    20 32  2  4  '.
.' 5  6  3  1 31 29 |  | 29 31  1  3  6  5 '.
|  7  8       28 27 |  | 27 28        8  7  |
|  9 10       26 25 |  | 25 26       10  9  |
| 11 12       24 23 |  | 23 24       12 11  |
| 13 15 17 19 22 21 |  | 21 22 19 17 15 13  |
|    14 16 18 20    |  |    20 18 16 14     |
 '-----------------'    '------------------'

PLCC32 memory pinout (same as DIP)

Top view, size 080 (see DIP pinouts for pin progresion)

          A12 A15 A16 A19 Vcc A18 A17
         _''__''__''__''__''__''__''__
       .'  4   3   2 ( 1) 32  31  30  |
     .'                               |
A7  [| 5                           29 |] A14
A6  [|                                |] A13
A5  [|                                |] A8
A4  [|                                |] A9
A3  [|                                |] A11
A2  [|                                |] OE#/Vpp
A1  [|                                |] A10
A0  [|                                |] CE#
Q0  [| 13                          21 |] Q7
     |___14__  __  __  __  __  __20___|
         ''  ''  ''  ''  ''  ''  ''
         Q1  Q2  GND Q3  Q4  Q5  Q6


49LF040 Low Pin Count flash
49LF00x Firmware Hub (FWH) PLCC flash
 x = 2:  2Mbit  256k x 8
     3:  3Mbit  384k x 8
     4:  4Mbit  512k x 8
     8:  8Mbit  1024k x 8
 
This flash contains sectored memory and a sector protection feature,
as well as 4 GPIO inputs. Device ID is selected by strapping the
ID[3:0] pins. See the SST datasheet for more details.

Caution: This flash also supports paralell programming mode, but the
pinout is NOT compatible with other 0x0 series flashes!

LPC and FWH pinouts are functionally identical, pin labels are
different. FWH is a subset of LPC interface, the flash commands are
identical. See Intel Low Pin Count (LPC) Interface Specification
(251289-001).  

                            
          FGPI2       RST#
              : FGPI3 :
              :   :   :  NC  Vdd CLK FGPI4
            _''__''__''__''__''__''__''__
          .'  4   3   2 ( 1) 32  31  30  |
        .'                               |
FGPI1  [| 5                           29 |] IC
FGPI0  [|                                |] Vss
  WP#  [|             49LF00x            |] NC
 TBL#  [|                                |] NC
  ID3  [|         FWH mode pinout        |] Vdd
  ID2  [|                                |] INIT#
  ID1  [|                                |] FWH4
  ID0  [|                                |] NC
 FWH0  [| 13                          21 |] RES
        |___14__  __  __  __  __  __20___|
            ''  ''  ''  ''  ''  ''  ''
            :   :   Vss :  RES RES RES
            :  FWH2    FWH3
           FWH1

LPC name   | FWH name |  Function
-----------+----------+----------------------------------------------
        IC             Mode switch (Low = FWH mode)
       INIT#           Reset (coupled internally to RST#)
       RST#            Reset
       TBL#            Top Block Lock, prevent bootblock programming
      ID[3:0]          Chip ID
 GPI[4:0]  FGPI[4:0]   General purpose inputs
 LAD[3:0]  FWH[3:0]    FWH interface IO
 LFRAME#   FWH4        FWH interface in (Chip select)
        WP#            Write protect
        RES            Reserved, Do not connect




See also:
----------
- ROMref.txt for older ROM/PROM chips:
https://smitdogg.mameworld.info/du/romref.txt
http://www.euro-arcade.de/files/romref.txt
http://www.armory.com/~rstevew/Public/Pgmrs/EPROM/ROMref.txt
https://polprog.net/papiery/ROMref.txt
- respective datasheets


Sources:
- respective datasheets
- https://www.batronix.com/shop/electronic/eprom-programming.html
  [access 19.08.2021]